Cache prefetching is a technique employed by computer processors to increase performance by preemptively fetching instructions and data from relatively slower storage locations (e.g., system memory) to faster storage locations (e.g., cache) before they are requested by the processors for execution. Prefetching enables portions of the memory access latency to be overlapped which increases processor performance by reducing the overall data access time. The factors to consider when designing or implementing a prefetcher include accuracy and timeliness. To be accurate means making good predictions about what is likely to be requested and therefore less resources are wasted on bad prefetches. An accurate prefetcher, however, typically utilizes algorithms that are relatively conservative and time-consuming. As such, prefetchers that are accurate tend to be slow and less aggressive in making prefetch predictions. On the other hand, a prefetcher that is timely, such as one that aggressively prefetches data ahead of a processor's access stream, tends to be less accurate because events are harder to predict the further they are out in time. Finding the right balance between accuracy and timeliness has long been the struggle plaquing engineers when trying to implement the “perfect” prefetching behavior.